The present invention relates to a method and an apparatus for laying out a power wiring of a semiconductor device.
Along with miniaturization and speeding-up (increasing operating frequency) of semiconductor integrated circuits, it becomes important to prevent voltage drops in a power wiring, or so-called IR drops, which cause a malfunction. The IR drop can be evaluated by modeling a power wiring layout and performing a DC (direct-current) analysis by using SPICE (Simulation Program with Integrated Circuit Emphasis) on a computer, for example.
Mitsuhashi et al. (“Power and Ground Network Topology Optimization for Cell Based VLSIs,” Proceedings of the 29th Design Automation Conference, pp. 524-529, 1992.) and Japanese Unexamined Patent Application Publication No. 03-204958 disclose analysis methods for dealing with IR drops purely mathematically as a nonlinear function problem. However, it is difficult to apply these analysis methods to a practical method for laying out a power wiring because the solution may not converge.
In the practical method for laying out a power wiring, when an IR drop violation exists as a result of a DC analysis, the DC analysis is performed again after widening the power wiring, for example. A sequence of operations are repeated until the IR drop violation is resolved.
Singh et al. (“Partition-Based Algorithm for Power Grid Design Using Locality,” IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, vol. 25, no. 4, pp. 664-677, April, 2006.) discloses a method for resolving the IR drop violation by widening the whole wiring in a certain region when the IR drop violation exists. Further, Japanese Unexamined Patent Application Publication No. 2000-349161 discloses a method for resolving the IR drop violation by providing an optimization target wiring and widening the whole optimization target wiring when the IR drop violation exists.